1. Field of the Invention
The present invention relates to a memory control system and a memory control circuit, and particularly to a memory control circuit having a plurality of external memories.
2. Description of Related Art
A system equipped with external memories such as SDRAM (Synchronous Dynamic Random Access Memory) and flash memory or SDRAM and SRAM (Static Random Access Memory) is known. Generally in such a system, a memory bus is shared among the external memories.
In DRAM devices, a SDRAM device is different from an EDO (Extended Data Out) DRAM device. In a SDRAM device, various commands can be input by combining control signals such as /RAS (Row Address Strobe) signal, /CAS (Column Address Strobe) signal and /WE (Write Enable) signal and so on.
One SDRAM device normally has a plurality of banks. Each bank is independently accessible in a SDRAM device. In such a SDRAM device, when a refresh operation is performed, all banks have to be precharged and the SDRAM device has to be in an idle state.
In order to perform the refresh operation smoothly, there are commands which are called “read (or write) command with auto precharge” so as to access SDRAM. Timing charts for such access are shown in FIGS. 6 and 7. For a read (or write) command with auto precharge, after retrieving a bank address (BA) and row address (A0 to A11) at a timing T61 in FIG. 6, a command indicating read with auto precharge (/CS, /RAS, /CAS, /WE, and A10) and a column address (A0 to A9, and A11) are retrieved at a timing T62 in FIG. 6. Then after a read operation to read data (write operation for writing data. See DG in FIG. 6), the accessed bank is precharged at a timing T63 in FIG. 6. Precharging accessed banks makes SDRAM to be an idle state. A read (or write) access with auto precharge makes the SDRAM to be always in an idle state. For example, when a read access by “read command with auto precharge” is performed, an accessed bank is precharged after each access, and the SDRAM device becomes an idle state. In case that a read access with auto precharge is performed, a SDRAM device is in an idle state after every access. Therefore, the refresh operation can be performed immediately when a refresh operation is requested.
However, a read (or write) access with auto precharge has a precharge operation and a bank activation operation in every access (see timings T63 and 64 in FIG. 6). These operations (precharge operation and bank activation operation) delay access speed of the SDRAM device. Therefore, there are commands called “read (or write) command without auto precharge”. According to read (or write) accesses without auto precharge, access speed of the SDRAM device can be improved. FIGS. 8 and 9 show timing chart for accessing without auto precharge.
In a read access without auto precharge, an accessed bank is not precharged after every access. If the next read (write) access is the read (write) access to the same bank which is accessed in the last read (write) access, the next read (write) access is performed without bank activation. If the next read (write) access is not the read (write) access to the same bank which is accessed in the last read (write) access, the bank corresponding to the next read access is activated, and the next read access is performed. In this case, even if the next read (write) access is not the read (write) access to the same bank which is accessed in the last read (write) access, the bank accessed in the last read (write) access is not precharged (see T83 in FIG. 8).
When a refresh operation is requested to the SDRAM device which is accessing without auto precharge, all banks have to be precharged because the SDRAM devise is not in an idle state due to accesses without auto precharge (see T93 in FIG. 9). The precharge of all banks can be performed according to one of the commands. In order to perform the precharge of all banks, the command is input via not only control terminals, such as /RAS terminal and /CAS terminal, but also address terminals (A10).
In a system equipped with external memories, a device accessing external memories includes a memory control circuit. The memory control circuit controls accesses to the external memories. In this kind of a system, an access request from a system LSI including CPU to SRAM or flash memory, an access request to SDRAM, and a refresh request to SDRAM are generated. The refresh request to SDRAM is generated at a constant interval regardless of an access request from CPU to a memory storage. As described above, the refresh request includes a signal which is input to a certain address terminal via address bus because the refresh request includes the command for precharging all banks. Therefore, if an access request to SRAM conflicts with the refresh request to SDRAM, an access to the SRAM is completed first, then the SDRAM is refreshed (see FIG. 10). Further, during a refresh period of the SDRAM, an access request to other external memory is suspended.
However it has been discovered that with the method which refreshes SDRAM after completing an access to SRAM, an address bus and a data bus (hereinafter referred to as a bus) cannot be utilized during the refresh period, because SRAM (or flash memory) and SDRAM share the bus. Accordingly it lowers efficiency in use of the bus and a transfer efficiency of a system.
A related art are disclosed in Japanese Unexamined Patent Application Publication No. 11-7763. In Japanese Unexamined Patent Application Publication No. 11-7763, a refresh operation is performed during an access is performed with a device except for a DRAM. However, Japanese Unexamined Patent Application Publication No. 11-7763 only discloses a conventional DRAM technology, and a refresh operation of a SDRAM is not disclosed.